Cadence Principal / Lead Application Engineer –前端验证热招中

铿腾电子

Cadence Principal / Lead Application Engineer –前端验证热招中

更多职位信息敬请关注Cadence公众微信平台：Cadence微招聘

If you have interest, PLS send your update CV to job_china@cadence.com

Principal / Lead Application Engineer (Front-end Verification)
Location: Shanghai / Beijing

Position Description:
- Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
- Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Providing technical expertise to address clients’ queries, which need expert involvement.
- Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:         
- 4~8 years’ experience in the following areas:
-  Design experience in Verilog/VHDL for IP or SoC chip level.
- HW verification with knowledge of System Verilog/VHDL and HDL simulators
- FPGA prototyping project experience
- Experience with hardware emulator or accelerator is a big advantage
-  Advanced Verification Methodology like UVM is a plus
- Knowledge of Unix and Linux is highly desired
- Strong verbal and written communication skills in English
- Strong teamwork skills with good human relationship